Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type

ABSTRACT

A semiconductor device includes a diffusion area formed in a semiconductor layer of a first conductive type. The diffusion area comprises first and second impurity diffusion areas of the first and second conductive types, respectively. The diffusion area has a first and second areas which are defined by an impurity concentration of the first and second impurity diffusion areas. A junction between the first and second area is formed in a portion in which the first and second impurity diffusion areas overlap each other. A period of the impurity concentration, in a planar direction of the semiconductor layer, of the first or second area is smaller than the maximum width, in the planar direction of the semiconductor layer, of the first and second impurity diffusion areas constituting the first or second area.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2001-395558, filed Dec. 27,2001, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a substrate structure of asemiconductor device having vertical power MISFETs (Metal InsulatorField Effect Transistors) each having a gate electrode formed on asemiconductor substrate, as well as a method of manufacturing thissubstrate structure.

2. Description of the Related Art

In a vertical power MIS (including a MOS (Metal Oxide Semiconductor) FETformed on a semiconductor substrate, a drain current flows between asource and drain electrodes formed on a top and bottom surfaces,respectively, of a semiconductor substrate. Such an element allows theresistance of a current passage to be reduced and is thus often used asa power device.

FIG. 34 shows the sectional structure of a super junction type MISFETcurrently put to practical use. A semiconductor substrate 100 iscomposed of a first semiconductor substrate and a second semiconductorsubstrate consisting of an epitaxial growth layer. The firstsemiconductor substrate, which functions as an N⁺ drain area 101,contacts with a drain electrode 105. The second semiconductor substrate,which functions as N⁻ drain areas 102, is provided with first P baseareas 103.

Second P base areas 106, which contact with the first P base areas 103,are formed under a surface of the second semiconductor substrate.Reference numerals 107, 108, 109, and 110 denote an N source area, agate insulating film, a gate area, and a source area.

The width of the P base area 103 and the N⁻ drain area 102 locatedbetween the P base areas 103 (a P and N type pillar layers,respectively) and the amounts of P and N type impurities contained inthese areas are optimally designed. Thus, if a reverse bias voltage isapplied to the MISFET, the P and N type pillar layers are depleted. Thisstructure enables on resistance to be reduced compared to other verticalMISFETs.

Other known examples of a MISFET improved so as to reduce the onresistance is described in U.S. Pat. No. 5,216,275 and Jpn. Pat. Appln.KOKAI Publication No. 2000-40822. In this U.S. Patent, pillar-likeP-type areas 7 (corresponding to 103 in FIG. 34 of the specification)connected to base areas are formed of trenches as shown in FIG. 2 or thelike. However, this patent does not clearly state that it can completelydeplete the pillar layers and reduce the on resistance. Further, thelatter publication describes the formation of both P and N layers in adrift layer by diffusion. However, a non-diffusion area remains betweenthe P and N layers. That is, an area with a low concentration remains ina substrate. Accordingly, in this structure, the maximum width of afirst or second diffusion area is larger than the thickness of a singleepitaxial growth layer. Thus, this patent fails to form a fine structurein a substrate planar direction and thus does not serve to reduce the onresistance.

The structure shown in FIG. 34 is formed as follows: First, a P typeimpurity diffusion area is formed in a first epitaxial growth layerformed on the first semiconductor substrate. Then, a P type impuritydiffusion area is formed in a second epitaxial growth layer formed onthe first epitaxial growth layer. This step is repeated for about fiveto seven layers. Then, the P type impurities in the epitaxial growthlayers are thermally diffused and thus connected together in a depthdirection to form the first P base area 103. At this time, adjacent Pimpurity diffusion areas must be formed at a specified distance so asnot to be joined together.

A MISFET having the structure shown in FIG. 34 allows the concentrationof impurities to be increased by reducing the widths of the P and N typepillar layers. This enables the on resistance to be further reduced.However, to reduce the widths of the pillar layers, it is necessary tojoin the impurity diffusion areas 102 together lengthwise with a smallamount of diffusion. As a result, the number of epitaxial growth layers(102 a to 102 k) increases as shown in FIG. 35, thus increasingmanufacturing costs.

Further, the manufacturing costs can be cut down by reducing the numberof epitaxial growth layers. However, in this case, the diffusion areas120 must be enlarged as shown in FIG. 36. Thus, the width of the pillarlayers increases, and the concentration of impurities decreases. Thismay degrade the on resistance.

The present invention is provided in view of these circumstances. It isan object of the present invention to provide a semiconductor devicehaving a drift area structure with a reduced pitch between each area (Ptype area) exhibiting the same polarity as that of a P type and acorresponding area (N type area) exhibiting the same polarity as that ofan N type and terminal area structure, in order to form MISFET elementshaving a fine structure and achieve complete depletion.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the present invention, there is provideda semiconductor device comprising a semiconductor layer of a firstconductive type and a diffusion area formed the semiconductor layer, thediffusion area comprising first impurity diffusion areas of the firstconductive type and second impurity diffusion areas of a secondconductive type which are alternately formed, the diffusion area havingfirst areas of the first conductive type and second areas of the secondconductive type which are defined by the impurity concentrations of thefirst and second impurity diffusion areas, respectively, wherein ajunction between each of the first areas and the corresponding secondarea is formed in a portion in which the corresponding first and secondimpurity diffusion areas overlap each other, and the period of theimpurity concentration, in a planar direction of the semiconductorlayer, of the areas selected from a group consisting of the first andsecond areas is smaller than the maximum width, in the planar directionof the semiconductor layer, of the first and second impurity diffusionareas constituting the selected areas.

According to a second aspect of the present invention, there is provideda method of manufacturing a semiconductor device, the method comprisinginjecting first impurities of a first conductive type and secondimpurities of a second conductive type into a surface of a semiconductorlayer of a first conductive type; and diffusing the first and secondimpurities to form a diffusion area, the diffusion area having a firstarea and a second area, the first and second areas defined by animpurity concentration of a first impurity diffusion area of the firstconductive type and a second impurity diffusion area of the secondconductive type, the first and second impurity diffusion areaoverlapping each other, and a period of the impurity concentration, in aplanar direction of the semiconductor layer, of an area selected from agroup consisting of the first and second areas being smaller than themaximum width, in the planar direction of the semiconductor layer, ofthe first and second impurity diffusion areas constituting the selectedareas.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a diagram showing the sectional structure of a semiconductordevice according to a first embodiment of the present invention;

FIGS. 2 and 3 are plan views of a surface of the semiconductor substrateshown in FIG. 1;

FIGS. 4 and 5 are plan views of a second semiconductor substrate onwhich a vertical MISFET, shown in FIG. 2 is formed;

FIGS. 6 to 9 are diagrams illustrating first and second diffusion layers13 and 14, shown in FIG. 1, and a method of manufacturing the same;

FIG. 10 is a plan view illustrating diffusion areas in the semiconductorsubstrate in FIGS. 8 and 9;

FIG. 11 is a graph showing an impurity concentration profile of thesemiconductor device in FIGS. 8 and 9;

FIG. 12 is a graph showing an NET concentration profile of thesemiconductor device in FIGS. 8 and 9;

FIG. 13 is a diagram showing the sectional structure of a semiconductordevice according to a second embodiment of the present invention;

FIGS. 14 to 16 are diagrams illustrating first and second diffusionlayers 13 and 14, shown in FIG. 13, and a method of manufacturing thesame;

FIG. 17 is a graph showing an impurity concentration profile of thesemiconductor device in FIG. 16;

FIG. 18 is a graph showing an NET concentration profile of thesemiconductor device in FIG. 16;

FIGS. 19 and 20 are graphs showing the concentration of impurities in adepth direction of a second semiconductor substrate 2;

FIG. 21 is a diagram showing the relationship between the epi-number andon resistance of the semiconductor substrate;

FIG. 22 is a diagram showing the sectional structure of a semiconductordevice according to a third embodiment of the present invention;

FIG. 23 is a graph showing an impurity concentration profile of thesemiconductor device in FIG. 22;

FIG. 24 is a graph showing an NET concentration profile of thesemiconductor device in FIG. 22;

FIG. 25 is a diagram showing the planar structure of a semiconductordevice according to a fourth embodiment of the present invention;

FIG. 26 is a diagram showing the sectional structure of thesemiconductor device in FIG. 25;

FIG. 27 is a diagram showing the planar structure of a semiconductordevice according to a fifth embodiment of the present invention;

FIG. 28 is a diagram showing the sectional structure of thesemiconductor device in FIG. 27;

FIG. 29 is a diagram showing the planar structure of a semiconductordevice according to a sixth embodiment of the present invention;

FIG. 30 is a diagram showing the sectional structure of thesemiconductor device in FIG. 29;

FIG. 31 is a diagram showing the planar structure of a semiconductordevice according to a seventh embodiment of the present invention;

FIG. 32 is a diagram showing the sectional structure of thesemiconductor device in FIG. 31;

FIG. 33 is a diagram showing the planar structure of a semiconductordevice according to a variation of the seventh embodiment of the presentinvention;

FIGS. 34 to 36 are sectional views of a conventional vertical MISFET;and

FIG. 37 is a graph showing a NET dose amount of the semiconductor devicein FIG. 10.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be described below withreference to the drawings. In the description below, components havingsubstantially the same functions and configurations are denoted by thesame reference numerals. Duplicate description will be given only whenrequired.

First Embodiment

A first embodiment will be described with reference to FIGS. 1 to 12.

FIG. 1 is a diagram showing the sectional structure of a semiconductordevice according to the first embodiment of the present invention. Thissemiconductor device is a vertical MISFET in which PN junctions areformed to extend in a depth direction. In each of the embodimentsdescribed below, for example, a first conductive type is N and, whereasa second conductive type is P.

As shown in FIG. 1, a semiconductor substrate (layer) 10 consisting of,for example, silicon is composed of a first semiconductor substrate 1and a second semiconductor substrate 2. The first semiconductorsubstrate 1 has impurities of a high concentration and an N typeconductivity. The second semiconductor substrate 2 is formed on thefirst semiconductor substrate 1 and has an N type conductivity with animpurity concentration lower than that of the first semiconductorsubstrate 1. The second semiconductor substrate 2 may be, for example, asingle epitaxial layer.

An N⁺ drain area 11 is formed in the first semiconductor substrate 1.The N⁺ drain area 11 is connected to a drain area 20 formed on a backsurface of the first semiconductor substrate 1.

An N⁻ drain area 12 which contacts with the N⁺ drain area 11 is formedin the second semiconductor substrate 2. An impurity diffusion area isformed in the N⁻ drain area 12 by diffusing impurities and has animpurity concentration higher than that of the second semiconductorsubstrate 2. This impurity diffusion area is composed of first diffusionareas 13 and second diffusion areas 14 formed inside the first diffusionarea 13. The first diffusion areas 13 have the same polarity as that ofthe N type. The second diffusion areas 14 have the same polarity as thatof the P type. The end of each of the second diffusion areas 14 isadjacent to the corresponding first diffusion area 13. The junctionbetween each of the first diffusion areas 13 and the correspondingsecond diffusion area 14 in a substrate planar direction isperpendicular to the substrates.

N and P type impurities are mixed in the first and second diffusionareas 13 and 14. In each portion of the impurity diffusion area, theconcentrations of these impurities define the first or second diffusionareas 13 or 14 as described below in detail. There are differences inimpurity concentration among the portions of the first and seconddiffusion areas 13 and 14. However, in terms of an average value, theimpurity concentration of the second semiconductor substrate 2 is set tobe greatly lower than those of the first and second diffusion areas 13and 14. More specifically, the impurity concentrations are set so thatthe concentration in the second semiconductor substrate is equal to orsmaller than one-fifths of those in the first and second diffusion areas13 and 14. Preferably, the concentration in the second semiconductorarea 2 is one-two-hundredth to one-fifth and more preferablyone-one-hundredth to one-fifth of those in the first and seconddiffusion areas.

The first diffusion areas 13 each function as an N drain area. Thesecond diffusion areas 14 each function as a first P base area.

Second P base areas 15 are formed on a surface of the semiconductorsubstrate 10 which is located on the respective first P base area(second diffusion area) 14. The second P base areas 15 are connected tothe respective first P base areas 14 and formed by diffusing impurities.N source areas 16 are formed inside each of the P base areas 15. Thefirst diffusion areas 13, the second P base areas 15, and the N sourceareas 16 are exposed from a main surface of the semiconductor substrate10 (the N⁻ drain areas 12 is normally passivated by an oxide film).

Gate electrodes 18 are each formed on the main surface of thesemiconductor substrate 10 via a gate insulating film 19 such as asilicon oxide film. The gate insulating film 19 and the gate electrode18 cover a part of the second P base area 15 and areas extending fromthe second P base area 15 to the N drain area 13 and the N source area16. Source-base leader electrodes (hereinafter referred to as “sourceelectrodes”) 17 are formed on the main surface of the semiconductorsubstrate 10. The source electrodes 17 each have a central portionformed on the P base area 15 and opposite ends each covering a part ofthe N source area 16.

FIGS. 2 and 3 are plan views of the structures of MISFET elements formedon a surface area of the semiconductor substrate 10. In these figures,the gate electrodes and the source electrodes are omitted. FIG. 1 is asectional view of a portion of the semiconductor device taken along theline I-I in FIG. 2. In the example shown in FIG. 2, lengthwise longMISFET elements (in FIG. 2, two) are formed in the semiconductorsubstrate. Further, in the example shown in FIG. 3, MISFET elements havea substantially square planar shape and are arranged on thesemiconductor substrate 10 in a matrix. The sectional structure is thesame as that shown in FIG. 1.

FIGS. 4 and 5 are plan views of a substrate surface illustrating thediffusion areas formed in the second semiconductor substrate 2. FIG. 4corresponds to FIG. 2, and FIG. 5 corresponds to FIG. 3. As shown inFIG. 4, the first diffusion area 13 and 14 are arranged adjacent to eachother in the N⁻ drain area 12, constituting the second semiconductorsubstrate 2. The adjacent first and second diffusion areas 13 and 14form a junction lengthwise in the plane of the semiconductor substrate10. Further, as shown in FIG. 5, the first and second diffusion areas 13and 14 have a substantially square planar shape. The first and seconddiffusion areas 13 and 14 are alternately arranged lengthwise andbreadthwise within the N⁻ drain area 12. The second diffusion areas 14are each surrounded by the first diffusion areas 13. The junctionbetween the second diffusion area 14 and the adjacent first diffusionarea 13 is formed along the periphery of the second diffusion area 14.

Now, the first and second diffusion areas 13 and 14 will be describedbelow in detail with reference to FIGS. 6 to 9. FIGS. 6 to 9 illustratethe first and second diffusion layers 13 and 14 in FIG. 1 and a methodof manufacturing the same. A method of forming these portions will alsodescribed. First, as shown in FIG. 6, the second semiconductor substrate2 is formed on the first semiconductor substrate 1. Then, a photo resist36 is formed on a surface of the second semiconductor substrate 2. Then,a photolithography step and an etching technique are used, formingopenings in the photo resist 36 at positions corresponding to those atwhich boron injection areas 31 are to be formed. The diameter of theseopenings is determined by the widths of the first and second diffusionareas 13 and 14 and the like. The appropriate diameter is, for example,between about 0.3 and 2.0 μm. Further, the appropriate pitch of theopenings is, for example, between about 6 and 18 μm. Then, boron (P typeimpurities) ions are injected through these openings at a dose Qd of 2to 10×10¹³ cm⁻². As a result, the boron injection areas 31 are formed atthe predetermined positions of a surface area of the secondsemiconductor substrate 2.

Then, as shown in FIG. 7, the photo resist 36 is removed. A photo resist37 is then formed on the surface of the semiconductor substrate 2. Then,a photolithography step and an etching technique are used, formingopenings each of which is located between the areas in which the boroninjection areas 31 are formed. The diameter of these openings isdetermined by the widths of the first and second diffusion areas 13 and14 and the like. The appropriate diameter is, for example, between about0.3 and 2.0 μm. Further, the appropriate pitch of the openings is, forexample, between about 6 and 18 μm. Then, phosphorus (N type impurities)ions are injected through these openings at a dose Qd of 2 to 10×10¹³cm⁻². As a result, the phosphorus injection areas 32 are formed at thepredetermined positions of the surface area of the second semiconductorsubstrate 2. This processing allows the boron injection areas 31 and thephosphorous injection areas 32 to be formed in the surface area of thesecond semiconductor substrate 2 so as to be alternately arranged. Whenthe photo resist is formed, a thin oxide film may be formed between thephoto resist and the silicon.

Then, as shown in FIG. 8, the semiconductor substrate 10 is thermallytreated, diffusing the boron and phosphorous in the boron injectionareas 31 and the phosphorous injection areas 32, respectively. As aresult, boron diffusion areas 33 and phosphorous diffusion areas 34 areformed. At this time, junctions 35 are each formed in the center of anoverlapping portion of the corresponding boron diffusion area 33 andphosphorous diffusion area 34 in a direction perpendicular to thesubstrate. As a result, as shown in FIG. 9, the first and seconddiffusion areas 13 and 14 are formed. The junction 35 is formed at amiddle position between the each center or the phosphorous diffusionarea 34 and the adjacent boron diffusion area 33 and the smaller a cellpitch becomes, the closer the junction 35 becomes to a center of thefirst and second diffusion areas.

FIG. 10 is a plan view illustrating the diffusion areas in thesemiconductor substrate shown in FIGS. 8 and 9. In the impuritydiffusion areas formed as shown in FIGS. 8 and 9, the P and N typeimpurities cancel each other in areas 39. As a result, N type areas 21and P type areas 22 are alternately arranged. The PN junctions 35 areformed perpendicularly in a depth direction of the substrate. Thoseportions of the P type areas 22 which are located in an area “A” lyingat the top of the semiconductor substrate 2 shown in FIG. 10 are shownoffset from the substrate surface for the convenience of description butactually rest on it. The first diffusion areas with a high phosphorousconcentration exhibit the same polarity as that of the N type. Thesecond diffusion areas 14 with a high phosphorous concentration exhibitthe same polarity as that of the P type.

FIGS. 11 and 12 are characteristic diagrams showing an impurity and NETconcentration profiles of the impurities injected into the semiconductorsubstrate shown in FIGS. 8 and 9, in a portion of the semiconductorsubstrate taken along line X-X in these figures. The boron andphosphorous (hereinafter collectively referred to as “impurities”)injected into the semiconductor substrate 10 are diffused and exhibit animpurity and NET concentration profiles such as those shown in FIGS. 11and 12. As shown in FIGS. 11 and 12, P type areas (having the samepolarity as that of the P type) and N type areas (having the samepolarity as that of the N type) are alternately formed. The adjacentindividual boron diffusion areas 33 are joined together and theconcentration distribution (B concentration profile) of the borondiffusion areas 33 in the planar direction of the semiconductorsubstrate 10 (hereinafter referred to as the “substrate planardirection”) has a period “a”.

The period “a” substantially corresponds to the period of concentrationof the impurities in the first or second diffusion area 13 or 14, or thepitch of the diffusion areas 13 or 14, or the spacing between thephosphorous or boron injection areas 32 or 31. These descriptions alsoapply to the P concentration profile. The junctions 35 are each formedat the position where the phosphorous (P) concentration profile equalsthe boron (B) concentration profile.

The boron injection areas 31 and the phosphorous injection areas 32 areformed, for example, under the above described conditions. As a result,the period “a” of the boron diffusion areas 33 and phosphorous diffusionareas 34 is smaller than the maximum diffusion length (diffusion width)of the individual diffusion areas 33 and 34 in the substrate planardirection. Thus, a high impurity concentration area extends widely inthe first and second diffusion areas 13 and 14.

The high impurity concentration area extending widely will now beexplained with examples. FIG. 37 shows a NET dose amount along the lineXI-XI in FIG. 10 and a comparison between the embodiment and a priorart. Only either of P profile and N profile is shown in the figure.Also, the solid line exhibits the embodiment and the broken line showsthe prior art. A concrete condition for the figure is that the period“a” is 8 μm in the embodiment and 161 m in the prior art. Otherconditions remain the same in both cases.

As shown in FIG. 37, an area (70% area) in which a concentration is 70%of the peak concentration extends over 50% of the first and seconddiffusion areas 13 and 14 in the embodiment, while 25% in the prior art.In a case of an area (50% area) in which the concentration is 50% of thepeak concentration extends over 65% of the first and second diffusionareas 13 and 14 in the embodiment, while 40% in the prior art. That is,an area in which a concentration is over 50% of the peak concentrationextends over 50% to 65% of the first and second diffusion areas 13 and14 in the embodiment.

According to the first embodiment, the first and second diffusion areas13 and 14 are formed in the second semiconductor substrate 2 with a lowimpurity concentration, using impurities formed by ion injection anddiffusion. The first and second diffusion areas 13 and 14 are defined bythe concentrations and overlapping portions in the second substrate 2.Thus, the first and second diffusion areas 13 and 14 can be formed to benarrower while avoiding joining the adjacent second diffusion areas 14together. This serves to provide a semiconductor device with reduced onresistance.

According to the first embodiment, the period a of impurityconcentration of each of the first and second diffusion areas 13 and 14is smaller than the maximum diffusion length of the boron diffusionareas 33 and phosphorous diffusion areas 34 in the substrate planardirection. Thus, junction 35 is formed at the vicinity of the center ofthe boron diffusion areas 33 and phosphorous diffusion areas 34. As aresult, most part of the first and second diffusion layers 13 and 14 areformed at the vicinity of the center of the phosphorous diffusion areas34 and the boron diffusion areas 33, and this part has a high impurityconcentration. Thus, the impurity concentration of the first diffusionareas 13, which constitute a current passage, is high while the MISFETis on. This serves to provide a semiconductor device with reduced onresistance. Further, narrow width (small period “a”) of the first andsecond diffusion layers 13 and 14 help these diffusion layers 13 and 14deplete completely. This serves to provide a semiconductor device with ahigh withstand voltage, while reducing a cell pitch.

Further, the balance of total sum of impurity concentrations in thefirst and second diffusion areas 13 and 14 is important to obtain a highwithstand voltage. According to the present application, adding an Ntype dopant during epitaxial growth conventionally forms N typeimpurities corresponding to the first diffusion areas 13. On the otherhand, an ion injection forms the first and second diffusion areas 13 and14 in the first embodiment. The ion injection improves concentrationcontrollability, thus allowing the balance to be maintained easily evenwith finer design.

Second Embodiment

A second embodiment will be described with reference to FIGS. 13 to 20.In the first embodiment, the second semiconductor substrate 2 iscomposed of, for example, a single epitaxial growth layer or the like.In contrast, a semiconductor device according to the second embodimenthas a structure in which the second semiconductor substrate 2 has aplurality of layers and in which PN junctions are formed to be deeper byrepeating the manufacturing method of the first embodiment.

FIG. 13 shows the sectional structure of the semiconductor deviceaccording to the second embodiment of the present invention. Thissemiconductor device is a vertical MISFET in which PN junctions areformed to extend in the depth direction. In the second embodiment, thesecond semiconductor substrate 2 is composed of a plurality of epitaxialgrowth layers consisting of, for example, silicon. The first and seconddiffusion areas 13 and 14 are formed by forming a plurality of differentimpurity diffusion areas in the respective layers and joining theimpurity diffusion areas with the same polarity together lengthwise. Asa result, the PN junctions are formed to be deeper than those in thefirst embodiment as shown in FIG. 13.

Now, with reference to FIGS. 14 and 15, detailed description will begiven of the second semiconductor substrate 2 and the first and seconddiffusion areas 13 and 14. FIGS. 14 and 15 are sectional viewsillustrating the first and second diffusion areas 13 and 14. Descriptionwill also be given of a method of forming these portions. In FIGS. 14and 15, the second semiconductor substrate 2 is formed by repeating asingle epitaxial layer configured as described in Embodiment 1, forexample, six times.

As shown in FIGS. 14 and 15, the second semiconductor substrate 2 iscomposed of a plurality of epitaxial layers (2 a to 2 f). Theseepitaxial layers 2 a to 2 f are formed as described below. First, theboron injection areas 31 and the phosphorous injection areas 32 areformed in the surface area of the first epitaxial layer 2 a as describedin the first embodiment. Then, the second epitaxial layer 2 b is formedon the first epitaxial layer 2 a. Then, the boron injection areas 31 andthe phosphorous injection areas 32 are formed in the surface area of thesecond epitaxial layer 2 b so as to join with the injection areas 31 and32, respectively, in the first layer 2 a lengthwise of the substrate.Subsequently, the above steps are repeated until the sixth layer 2 f isformed. Then, the phosphorous diffusion areas 34 and the boron diffusionareas 33 are formed from the phosphorous and boron injection areas,respectively, in each layer by thermal treatment.

The thermal treatment makes the first and second diffusion layers 13 and14 from the phosphorous diffusion areas 34 and the boron diffusion areas33. PN junctions are formed in the semiconductor substrate 10 in thevertical direction.

Further, in FIGS. 14 and 15, the thickness of a single epitaxial growthlayer constituting the second semiconductor substrate 2 (the period ofthe concentration of impurities in the substrate depth direction) isdefined as “b”. Further, the diffusion length of P type impurities(boron) or N type impurities (phosphorous) in the depth direction isdefined as “r”, and then the diffusion length (spread width) of P typeimpurities or N type impurities in the substrate planar direction isdefined as “L”. In this case, relationships shown below are establishedbetween the periods “a” and “b” of the boron diffusion area 33 orphosphorous diffusion area 34, between “a” and “L”, and between “b” and“r”, respectively.L>a  (1)r>b/2  (2)

Now, the diffusion structure of the second semiconductor substrate 2will be described with reference to FIGS. 17 to 20. FIG. 17 is acharacteristic diagram showing an impurity concentration profile of thatportion of the second semiconductor substrate 2 shown in FIG. 16 takesalong the line XVII-XVII. The first and second diffusion areas 13 and 14are formed at a pitch (period) “a”. FIG. 18 is a characteristic diagramin which the impurity concentration profile shown in FIG. 17 is replacedwith a NET concentration profile.

FIG. 19 is a characteristic diagram showing the impurity concentrationof a portion of the second semiconductor substrate 2 taken along theline XIX-XIX. The P type impurity concentration is higher than the Ntype impurity concentration in this area, and the area exhibits thesecond diffusion area 14 which has the same polarity as that of the Ptype.

FIG. 20 is a characteristic diagram showing the impurity concentrationof a portion of the second semiconductor substrate 2 taken along theline XX-XX.

The N type impurity concentration is higher than the P type impurityconcentration in this area, and the area exhibits the first diffusionarea 13 which has the same polarity as that of the N type. As shown inFIGS. 19 and 20, the concentrations of the N and P type impurities varywith the period “b”.

Now, description will be given below of a comparison of the secondembodiment with a conventional example. FIG. 21 is a characteristicdiagram showing the relationship between the number of epitaxial growthscarried out to form the epitaxial growth layers (hereinafter referred toas the “epitaxial number”) and on resistance of the semiconductorsubstrate. The epitaxial number affects on resistance of the element, asshown in FIG. 21. The axis of abscissas in FIG. 21 indicates theepitaxial number, while the axis of ordinates indicates the onresistance Ron (mΩcm²) Ron denotes the on resistance normalized by thearea of the FET. The characteristic curve in FIG. 21 shows thedependence of the on resistance on the epitaxial number in a methoddescribed in the second embodiment (a fine multi-epitaxial method) andin a method (normal multi-epitaxial method) according to theconventional example shown in FIGS. 34 to 36.

As described in the first embodiment, narrowing the first and seconddiffusion layers 13 and 14 can increase the impurity concentrations ofthese diffusion layers 13 and 14, and thus the on resistance can bereduced. This is shown in FIG. 21. As shown in this figure, with thesame epitaxial number, the method according to the present embodimentallows the first and second diffusion layers 13 and 14 to be narrowed.Accordingly, the on resistance thus obtained is half of that obtained inthe conventional example. The figure also indicates that the same onresistance can be accomplished using half the epitaxial number comparedto the conventional example.

According to the second embodiment, the second semiconductor substrate 2is configured similarly to the first embodiment. Thus, the secondembodiment produces effects similar to those of the first embodiment.

Further, the second embodiment 2 has a structure in which a plurality ofepitaxial layers are stacked together a number of times. Furthermore,the concentration period “a” of each first diffusion area 13 or seconddiffusion area 14 in the substrate planar direction is greater than theconcentration period “b” (the thickness of a single epitaxial layer) inthe substrate depth direction (a>b). This also serves to increase theimpurity concentrations of the first and second diffusion areas 13 and14 and provide a semiconductor device with a high withstand voltage andreduced on resistance, as in the first embodiment. It is noted that theadvantages brought about by the second embodiment can be obtained whilethe relationship between “a” and “b” is a<b. However, design andimplementation can be performed easily when the relationship is a>b thana<b.

Further, the second semiconductor substrate 2 having suchcharacteristics has a structure in which a plurality of epitaxial layersare stacked together a number of times. Thus, if a semiconductor deviceis formed with the same epitaxial number as that in the conventionalexample, about half the on resistance is obtained compared to theconventional example. On the other hand, the same on resistance can beaccomplished using half the epitaxial number compared to theconventional example.

Third Embodiment

A third embodiment will be described with reference to FIGS. 22 to 24.In addition the structure of the second embodiment, the third embodimenthas a structure in which diffusion areas are further repeatedly formedbreadthwise.

FIG. 22 shows the sectional structure of a semiconductor deviceaccording to the third embodiment of the present invention, i.e. thesectional structure of a semiconductor substrate provided with verticalMISFET elements. As shown in FIG. 22, for example, three seconddiffusion areas (P type areas) 14 are formed inside the semiconductorsubstrate 2 so as to be each sandwiched between the first diffusionareas (N type areas) 13. It is possible to further increase the numberof second diffusion areas 14.

FIG. 23 shows an impurity concentration profile of a portion of thesemiconductor device taken along the line XXIII-XXIII in FIG. 22. FIG.24 shows a NET concentration profile indicating the total concentrationdistribution of the same portion.

According to the third embodiment, the second embodiment 2 and the firstand second diffusion areas 13 and 14 are structured similarly to thesecond embodiment. Thus, the third embodiment produces effects similarto those of the first and second embodiments.

Furthermore, according to the third embodiment, three or more seconddiffusion areas 14 are formed. Thus, the MISFET elements can be formedwith a high density. This provides a semiconductor device that can behighly integrated.

Fourth Embodiment

A fourth embodiment relates to a structure used in addition to those ofthe first to third embodiments, and is directed to a terminal structureof a semiconductor device. As described above, according to the first tothird embodiments of the present invention, the concentration of thesecond semiconductor substrate 2 can be maintained at a low level. Thisis because, injecting ions into an N type semiconductor substrate with alow concentration makes N and P type pillar-like diffusion layers asopposed to injecting P type impurities into an N type semiconductorsubstrate with a high concentration in the conventional example.

FIG. 25 shows the planar structure of a semiconductor device accordingto the fourth embodiment of the present invention. FIG. 26 shows thesectional structure of a portion of the semiconductor device taken alongthe line XXVI-XXVI in FIG. 25. In FIGS. 25 and 26, a portion of thesemiconductor device provided with a MISFET has a structure similar tothat in the second or third embodiment. In addition, in FIG. 26, thefirst impurity diffusion layers 13, the N source areas 16, the gateelectrodes 18, and insulating films 44 and N⁺ stopper electrodes 43,described later, are omitted.

As shown in FIGS. 25 and 26, the first and second diffusion layers 13and 14 are not formed near a terminal of the semiconductor device. Thatis, the first and second diffusion layers 13 and 14 are spaced from theterminal of the semiconductor device. For example, three guard rings 41of an appropriate width are formed around a MISFET element atpredetermined intervals. The guard rings 41 are each formed on thesurface of the second semiconductor substrate 2 in the area (hereinafterreferred to as the “terminal area of the semiconductor device”) betweenthe terminal of the MISFET element, i.e. the corresponding end of thefirst diffusion layer 13 and the corresponding end of the semiconductordevice. Further, the guard rings 41 are formed of an impurity diffusionarea of the second conductive type.

An N⁺ stopper layer 42 with a high concentration is formed at the end ofthe semiconductor device and on the surface of the second semiconductorsubstrate 2. An N⁺ stopper electrode 43 is formed on the N⁺ stopperlayer 42. An insulating film (interlayer film) 44 is formed in theterminal area of the semiconductor device and on the surface of thesecond semiconductor substrate 2.

The effects of the fourth embodiment will be described below. In theterminal area of the semiconductor device, a depletion layer must beformed to an appropriate extent in order to obtain a withstand voltagein this area. However, if a semiconductor layer (corresponding to thesecond semiconductor substrate 2 in the present embodiments) providedwith N and P type diffusion layers has a high concentration as in theprior art, a depletion layer extending to the terminal is notsufficiently formed. Accordingly, separate measures are required inorder to sufficiently extend the depletion layer. However, according tothe first to third embodiments of the present application, the impurityconcentration of the second semiconductor substrate 2 can be reduced.Consequently, it is possible to form a depletion layer extending to theterminal of the semiconductor without any special measures. Thus, when,in addition to such a structure, the guard rings 41 are formed as in thefourth embodiment, a depletion layer can be formed to a larger extent.

According to the fourth embodiment, the second semiconductor substrate 2and the first and second diffusion layers 13 and 14 are structuredsimilarly to the first to third embodiments. The fourth embodiment thusproduces effects similar to those of the first to third embodiments.

Furthermore, according to the fourth embodiment, the terminal area notprovided with the first or second diffusion layers 13 or 14 is formed,and the second semiconductor substrate 2, provided with the first andsecond diffusion layers 13 and 14, have a low impurity concentration.Thus, a depletion layer extending to the terminal of the semiconductordevice is formed in this area. This serves to provide a semiconductordevice with a high withstand voltage. Furthermore, the formation of theguard rings 41 allows a depletion layer to be formed to a larger extent.

Fifth Embodiment

A fifth embodiment relates to a variation of the fourth embodiment.

FIG. 27 shows the planar structure of a semiconductor device accordingto the fifth embodiment of the present invention. FIG. 28 shows thesectional structure of a portion of the semiconductor device taken alongthe line XXVIII-XXVIII in FIG. 27. As shown in FIGS. 27 and 28, aninsulating film 51 with an appropriate number of (in FIG. 28, three, forexample) steps is formed in the terminal area of the semiconductordevice and on the surface of the second semiconductor substrate 2. Theheight of each step of the insulating film increases toward the terminalof the semiconductor device. A field plate electrode 52 extends on theinsulating film 51. The field plate electrode 52 is connected to thesource electrode 17 or the gate electrode 18 (in FIG. 28, it isconnected to the source electrode 17). An end of the field plateelectrode 52 is arranged on, for example, a portion of the insulatingfilm 51 which is highest. The number of steps of the insulating film 51is not limited to three. Furthermore, the insulating film 51 may beinclined instead of having the steps.

According to the fifth embodiment, the second semiconductor substrate 2and the first and second diffusion layers 13 and 14 are structuredsimilarly to the first to fourth embodiments. The fifth embodiment thusproduces effects similar to those of the first to fourth embodiments.

Moreover, according to the fifth embodiment, the insulating film 51,which is thicker toward the end of the semiconductor device, is formedon the surface of the second semiconductor substrate 2. Further, thefield plate electrode 52, connected to the source electrode 17 or thegate electrode 18, is formed on the insulating film 51. Thus, electricfields concentrate in a thicker part of the insulating film 51 which islocated closer to the end of the field plate electrode 52. Theinsulating film has a higher withstand voltage than the semiconductorsubstrate such as silicon, thus serving to provide a semiconductordevice having a high withstand voltage as a whole.

Sixth Embodiment

As described above, for a semiconductor device in which a semiconductorlayer (corresponding to the second semiconductor substrate 2 in thepresent embodiments) provided with N and P type diffusion layers has ahigh concentration, measures are required in order to sufficiently forma depletion layer extending to the terminal of the semiconductor device.One possible method for this purpose is to form an impurity diffusionlayer in the semiconductor layer which does not function as a MISFET.

FIG. 29 shows the planar structure of a semiconductor device accordingto a sixth embodiment of the present invention. FIG. 30 shows thesectional structure of a portion of the semiconductor storage devicetaken along the line XXX-XXX. As shown in FIGS. 29 and 30, substantiallylinear third diffusion layers 61 and fourth diffusion layers 62 areformed in the second semiconductor substrate 2. The third diffusionlayers 61 are of the N type, while the fourth diffusion layers 62 are ofthe P type. The third diffusion layers 61 and the fourth diffusionlayers 62 reach, for example, the N⁻ drain area 12 located at an end ofthe semiconductor substrate 10 and are alternately formed. The third andfourth diffusion layers 61 and 62 may be formed in a steps in which thefirst and second diffusion layers 13 and 14 are formed at the same time.Accordingly, the third and fourth diffusion layers 61 and 62 areconfigured substantially similarly to the first and second diffusionlayers 12 and 13.

In the terminal area of a semiconductor device configured as describedabove, depletion layers are formed along the junctions between the thirddiffusion layers 61 and the fourth diffusion layers 62. Accordingly, inthe planar breadthwise direction and a depth direction of thesemiconductor substrate, depletion layers are formed so as to correspondto the positions at which the third and fourth diffusion layers 61 and62 are formed. In this regard, the planar shapes of the third and fourthdiffusion layers 61 and 62 (the shapes in FIG. 29) are determinedaccording to the positions at which depletion layers are to be formed.These planar shapes are not limited to those shown in FIG. 29.

Now, the effects of the sixth embodiment will be described. In thepresent embodiments, which allow the maintenance of impurityconcentration of the second semiconductor substrate 2 at a low level, acommon structure such as the one shown in the fourth and fifthembodiments is used to obtain the desired withstand voltage. However, ifsuch a method still fails to form depletion layers to a sufficientextent, the sixth embodiment can be effectively applied.

Furthermore, the impurity concentration of the second semiconductorsubstrate 2 can be reduced, so that the concentration of impurities canbe controlled more easily than in the case in which impurity diffusionlayers are formed in a semiconductor substrate with a high impurityconcentration.

According to the sixth embodiment, the second semiconductor substrate 2and the first and second diffusion layers 13 and 14 are structuredsimilarly to the first to fourth embodiments. The sixth embodiment thusproduces effects similar to those of the first to fourth embodiments.

According to the sixth embodiment, furthermore, the third and fourthdiffusion layers 61 and 62, which are used to form depletion layers, areformed inside the second semiconductor substrate 2 with a low impurityconcentration. Thus, the third and fourth diffusion layers 61 and 62 canbe formed easily and depletion layers can be formed to a larger extent,which serves to provide a semiconductor device with a high withstandvoltage.

Further, the third and fourth diffusion layers 61 and 62 can be formedwhen the first and second diffusion layers 13 and 14 are formed at thesame time. Therefore, a semiconductor device with a high withstandvoltage can be obtained by fewer manufacturing steps than ones in thefourth and fifth embodiments.

Seventh Embodiment

A seventh embodiment relates to a variation of the sixth embodiment.

FIG. 31 shows the planar structure of a semiconductor device accordingto the seventh embodiment of the present invention. FIG. 32 shows thesectional structure of a portion of the semiconductor device taken alongthe line XXXII-XXXII in FIG. 31. As shown in FIGS. 31 and 32, the fourthdiffusion layers 62 are formed in the respective third diffusion layers61 in the terminal area, for example, so as to radiate from the centerof the semiconductor device.

The third and fourth diffusion layers 61 and 62 are formed to meet thefollowing equation:0.5<(S1×Qd1)/(S2×Qd2)<1.5  (3)

where Qd1: dose of impurities used when ions are injected to form thethird diffusion layers 61,

Qd2: dose of impurities used when ions are injected to form the fourthdiffusion layers 62,

S1: area in which ions are injected to form the third diffusion layers61, and

S2: area in which ions are injected to form the fourth diffusion layers62.

By forming the third and fourth diffusion layers 61 and 62 so as to meetEquation (3), depletion layers are extended far from the junctionsbetween the diffusion layers 61 and the diffusion layers 62. Thus, thethird and fourth diffusion layers 61 and 62 may be formed, for example,like a lattice as shown in FIG. 33 as long as the Equation (3) is met.This lattice shape need not lie along the edges of the semiconductordevice but may extend at an appropriate angle from them.

According to the seventh embodiment, the second semiconductor substrate2 and the first and second diffusion layers 13 and 14 are structuredsimilarly to the first to fourth embodiments. The seventh embodimentthus produces effects similar to those of the first to fourthembodiments.

Furthermore, according to the seventh embodiment, the third and fourthembodiments 61 and 62, used to form depletion layers, are formedradially or like a lattice under the predetermined conditions. Depletionlayers can be formed to a large extent in the terminal area. This servesto provide a semiconductor device with a high withstand voltage.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. (canceled)
 2. A method of manufacturing a semiconductor devicecomprising: injecting first impurities of a first conductive type andsecond impurities of a second conductive type into a surface of a firstsemiconductor layer of a first conductive type at a plurality of points;and diffusing the first and second impurities to form a first diffusionarea of the first conductive type and a second diffusion area of thesecond conductive type, the first diffusion area and the seconddiffusion area being defined by a first concentration profile of thefirst impurities and a second concentration profile of the secondimpurities, a junction between the first diffusion area and the seconddiffusion area being formed where a concentration of the firstimpurities and a concentration of the second impurities are same, aperiod of the first concentration profile in a planar direction of thefirst semiconductor layer being smaller than a maximum diffusion widthof the first impurities in the planar direction of the firstsemiconductor layer.
 3. The method according to claim 2, furthercomprising: forming a second semiconductor layer of the first conductivetype on the first semiconductor layer after injecting the first andsecond impurities into the first semiconductor layer; injecting thirdimpurities of the first conductive type into the second semiconductorlayer over points where the first impurities are injected in the firstsemiconductor layer; and injecting fourth impurities of the secondconductive type into the second semiconductor layer over points wherethe second impurities are injected in the first semiconductor layer,wherein diffusing the first and second impurities further includesdiffusing the first to fourth impurities until the first diffusion areaand the second diffusion area extend over the first semiconductor layerand the second semiconductor layer.
 4. The method according to claim 2,wherein the first impurities include phosphorous and the secondimpurities include boron.
 5. The method according to claim 3, whereinthe first impurities and the third impurities include phosphorous andthe second impurities and the fourth impurities include boron.
 6. Amethod of manufacturing a semiconductor device comprising: injectingfirst impurities of a first conductive type into a first semiconductorlayer of the first conductive type at least at two first points;injecting second impurities of a second conductive type into the firstsemiconductor layer between the two first points; and diffusing thefirst impurities and the second impurities until a first concentrationprofile of the first impurities having a first period and a secondconcentration profile overlap to form a first diffusion area and asecond diffusion area which are defined by the first concentrationprofile and the second concentration profile, the first period beingsmaller in a planar direction of the first semiconductor layer than amaximum diffusion width of the first impurities.
 7. The method accordingto claim 6, wherein the first impurities include phosphorous and thesecond impurities include boron.
 8. The method according to claim 6,further comprising forming the first semiconductor layer by epitaxialgrowth above a semiconductor substrate before injecting the firstimpurities and the second impurities, the first semiconductor layerhaving an impurity concentration equal to or less than a fifth of animpurity concentration of the first diffusion area.
 9. The methodaccording to claim 6, further comprising: forming a second semiconductorlayer of the first conductive type on the first semiconductor layerafter injecting the first impurities and the second impurities into thefirst semiconductor layer; injecting third impurities of the firstconductive type into the second semiconductor layer over points wherethe first impurities are injected in the first semiconductor layer; andinjecting fourth impurities of the second conductive type into thesecond semiconductor layer over points where the second impurities areinjected in the first semiconductor layer, wherein diffusing the firstimpurities and the second impurities further includes diffusing thefirst to fourth impurities until the first diffusion area and the seconddiffusion area extend over the first semiconductor layer and the secondsemiconductor layer.
 10. The method according to claim 9, wherein thefirst impurities and the third impurities include phosphorous and thesecond impurities and the fourth impurities include boron.
 11. Themethod according to claim 9, further comprising forming the firstsemiconductor layer by epitaxial growth above a semiconductor substratebefore injecting the first impurities and the second impurities, thefirst semiconductor layer having an impurity concentration equal to orless than a fifth of an impurity concentration of the first diffusionarea, wherein forming a second semiconductor layer includes forming byepitaxial growth the second semiconductor layer having an impurityconcentration equal to or less than a fifth of an impurity concentrationof the first diffusion area.
 12. The method according to claim 6,wherein injecting the first impurities includes injecting the firstimpurities at a plurality of points, injecting the second impuritiesincludes injecting the second impurities at a plurality of pointsbetween the plurality of points where the first impurities are injected,the second concentration profile has a second period which is smaller inthe planar direction of the first semiconductor layer than a maximumdiffusion width of the second impurities, and plural of said firstdiffusion area and said second diffusion area are formed in the firstsemiconductor layer.
 13. The method according to claim 6, wherein theplurality of points where the first impurities are injected are apartfrom each other at 6 to 18 μm and the plurality of points where thesecond impurities are injected are apart from each other at 6 to 18 μm.14. The method according to claim 6, further comprising forming a thirddiffusion area in an end region which is formed between an end of anfirst semiconductor layer and a MISFET region where the plural of thefirst diffusion area and the plural of the second diffusion area areformed.
 15. The method according to claim 6, further comprising: forminga base area of the second conductive type in a surface of the firstsemiconductor layer and connected to the second diffusion area; forminga source area of the first conductive type in the base area; forming asource electrode on the surface of the first semiconductor layer so asto cover a part of the source area; forming a gate electrode on thesurface of the first semiconductor layer with a gate insulating filminterposed therebetween so as to cover a part of the base area, sourcearea, and first diffusion area; forming an insulating film in the endregion and on the surface of the first semiconductor layer, theinsulating film having a height increasing toward the end of the firstsemiconductor layer; and forming a first electrode on the insulatingfilm, the first electrode being connected to the source electrode or thegate electrode.
 16. The method according to claim 6, further comprisingforming a third diffusion area and a fourth diffusion area havingsubstantially a same structure as the first diffusion area and thesecond diffusion area, respectively, in an end region which is formedbetween an end of an first semiconductor layer and a MISFET region wherea plural of the first diffusion area and a plural of the seconddiffusion area are formed
 17. The method according to claim 6, whereinthe third diffusion area and the fourth diffusion area meet:0.5<(S1×Qd1)/(S2×Qd2)<1.5 where Qd1: dose of impurities used when ionsare injected to form the third diffusion area, Qd2: dose of impuritiesused when ions are injected to form the fourth diffusion area, S1: areain which ions are injected to form the third diffusion area, and S2:area in which ions are injected to form the fourth diffusion area. 18.The method according to claim 16, wherein the third diffusion area andthe fourth diffusion area are formed to be substantially linear in aplane of the first semiconductor layer.
 19. The method according toclaim 16, wherein the third diffusion area and the fourth diffusion areaare formed to be substantially radial in a plane of the firstsemiconductor layer.
 20. The method according to claim 16, wherein thethird diffusion area and the fourth diffusion area form a substantiallattice in a plane of the first semiconductor layer.
 21. A method ofmanufacturing a semiconductor device comprising: forming a firstsemiconductor layer by epitaxial growth on a semiconductor substrate;injecting first impurities of the first conductive type and secondimpurities of a second conductive type into the first semiconductorlayer, points where the first impurities are injected and points wherethe second impurities are injected being apart from each other;conducting formation of an i-th semiconductor layer on the (i−1)-thsemiconductor layer by epitaxial growth and i-th injection of the firstimpurities and the second impurities into the i-th semiconductor layerover points where the first impurities and the second impurities areinjected in the (i−1)-th semiconductor layer respectively, i being anatural number at least two, a set of the formation of an i-thsemiconductor layer and the i-th injection being repeated with i=i+1 forevery set until n-th semiconductor layer is formed and n-th injection isconducted, n being a natural number at least two; diffusing the firstimpurities and the second impurities to form a first diffusion area ofthe first conductive type and a second diffusion area of the secondconductive type, the first diffusion area and the second diffusion areaextending over the first semiconductor layer to the n-th semiconductorlayer, the first diffusion area and the second diffusion area beingdefined by a first concentration profile of the first impurities and asecond concentration profile of the second impurities, a junctionbetween the first diffusion area and the second diffusion area beingformed where a concentration of the first impurities and a concentrationof the second impurities are same.
 22. The method according to claim 21,wherein the first impurities include phosphorous and the secondimpurities include boron.
 23. The method according to claim 21, whereinthe first semiconductor layer to the n-th semiconductor layer have animpurity concentration equal to or less than a fifth of an impurityconcentration of the first diffusion area.